The present invention relates to a semiconductor device operated in a predetermined mode, which is selected from a plurality of modes, and a method for controlling such a semiconductor device.
Recent semiconductor devices are provided with a plurality of operation modes and are operated in a selected one of the modes. For example, in a semiconductor device, a user sets the desired operation mode by breaking a non-reciprocal device, such as a fuse. The semiconductor is manufactured in a state storing information indicating the set operation mode.
There are semiconductor devices (DRAMs) in the prior art that are provided with a partial refresh mode, which partially refreshes memory cells, or multiple low power consumption modes. In such a DRAM, a mode setting signal, which is input via an external terminal, sets the partial refresh section or the power down method.
FIG. 1 shows a first example of a prior art DRAM that executes a program to set the operation mode. A program mode signal/PE is provided to a program circuit 53 through an external terminal 51. An address code Add is provided to the program circuit 53 via an external terminal 52. The program circuit 53 retrieves an address code Add when the program mode signal/PE goes high. A decoder 54 determines the section that is to be refreshed in accordance with the retrieved address code Add. The main circuit 55 includes a memory core 55a for storing data. The main circuit 55 refreshes a predetermined section of the memory core 55a. The predetermined section is selected in accordance with a section selection signal.
The first example of the prior art DRAM requires the exclusive external terminals 51 and 52, which are not used during normal operation, and an exclusive circuit for executing programs. As a result, the system employing the DRAM and the control of the system are complicated. Due to the use of the exclusive circuit, the exclusive program cannot be controlled with a normal controller. The execution of the mode setting program is performed prior to normal operations even when the refreshing section does not have to be changed. In such a case, the program execution consumes unnecessary processing time.
To solve this problem, a DRAM may be provided with a fuse circuit. In this case, the mode is set by the information that is stored when the fuse circuit is broken. FIG. 2 illustrates a second example of a prior art semiconductor device (DRAM) that sets the operation mode in accordance with a setting code of the fuse circuit 57. The fuse circuit 57 includes a plurality of fuses 57a. The fuse circuit 57 provides a decoder 54 with a setting code that is in accordance with the breakage pattern of the fuses 57a. The decoder 54 determines the section that is to be refreshed in accordance with the setting code and provides the main circuit 55 with the section selection signal. A predetermined section of the selected memory core 55a is refreshed in accordance with the section selection signal.
However, in the DRAM of FIG. 2, once an operation mode is set, the operation mode cannot be changed. Thus, such DRAM cannot be used by one who wishes to change the operation mode after it is set.